The fabrication of modern circuits typically includes several steps. Integrated circuits are first fabricated on a semiconductor wafer, which contains multiple duplicated semiconductor chips, each comprising integrated circuits. The semiconductor chips are then cut from the wafer and packaged. The packaging processes have two main purposes: to protect delicate semiconductor chips; and to connect interior integrated circuits to exterior pins.
In conventional packaging processes, semiconductor chips are mounted on a module substrate using flip-chip bonding or wire bonding. Underfill is used to prevent cracks from being formed in solder bumps or solder balls, wherein cracks are typically caused by thermal stresses.
With the increasing demand for more functions, system in package (SiP) technology, in which two or more chips are packaged on one module substrate, has increasingly been used. With a high degree of integration at the module level, the electrical performance is improved due to the shortened connecting path between components. By using SiP, package design becomes more flexible and less complex. Time-to-market is also reduced for product upgrades.
SiP, however, has a greater package size than single chip packages. As a result, greater stress is introduced. Furthermore, the non-uniformity in package stress distribution becomes more severe. Due to the greater stress in local regions, SiP packages are more prone to failures. Possible failures in a SiP package include bump cracking, substrate cracking, low-k material or underfill delaminating, BGA ball cracking, etc. These failures cannot be solved even by using advanced substrates, for example, organic substrates formed of materials with low coefficients of thermal expansion (CTE) (for core and build-up layers). As is known in the art, advanced substrates are introduced for enhanced electrical performance in packages, but are also expected to reduce stresses in the packages.
Accordingly, what is needed in the art are new structures and/or packaging schemes for SiP packages to take advantage of the benefits associated with the greater degree of integration while at the same time overcoming the deficiencies of the prior art.